Improvements in data processing systems have generally been directed at improvement either of the average time required to execute a given instruction or reduction in cost of the equipment required to perform such an instruction. One design tradeoff which has typically been made is that of performance versus price for units of memory for the storage of data. For example, tape memory is traditionally slower and less expensive than disk memory. Disk memory in turn is available in several types; the selection of any one type involves a performance/price tradeoff. Disk memory is slower but less expensive than solid-state memory which itself is available in several types, the selection of which again involves a performance/price tradeoff. Thus, it continues to be a need of the art to provide cheaper, faster memories or, failing that, to improve the efficiency of presently existing memory types. The present invention relates to an improvement of the second type. In particular, the invention involves apparatus and methods of operation thereof for reducing the average time necessary for a host central processing unit (CPU), which typically comprises an arithmetic and logic unit and a main memory unit for retention of the instructions and data currently being operated on, to obtain data stored on a less expensive long-term data storage device, such as a magnetic disk or tape drive unit.
Delays in memory access occur due to mechanical limitations of the apparatus. For example, in the case of a disk drive, in general, plural disks rotate at a fixed speed past read/write heads which may either be stationary with respect to the disk or move radially back and forth with respect to the disk in order to juxtapose the heads to various portions of the disk surfaces. In either case, there is a finite average time (termed "access time") required for a particular data record to be located and read from the disk into a faster form of memory, typically a solid state main memory included in the host computer. The delay may involve the "seek" time required for the head to be moved radially to the particular "track" selected, as well as "latency" time required for the disk to rotate with respect to the head until the beginning of the particular record sought is juxtaposed to the head for reading or writing.
Accordingly, it is an object of the present invention to provide a memory subsystem in which the average time required for a record sought to be transferred to the main memory system of a host computer is significantly reduced.
Prior art data processing systems typically comprise a host computer and long term memory storage means including such devices as magnetic disk memory units and magnetic tape units. Communication from the host computer to the disk or tape memory subsystem is generally made via a "channel" which physically comprises a defined set of signal connections over which all information--including data as well as commands, control signals, status signals, request signals and the like--must pass. In order that a memory subsystem can be marketable, it must "interface" or mate directly with a channel identical with those with which prior memory subsystem mated, thus being "plug compatible" with the host computer.
It is an object of the present invention to provide an improved memory subsystem which is "plug-compatible" with a prior art host computer.
Similarly, it is desirable if not commercially requisite that any data subsystem not require modification to the host programming instructions or "software" upon connection, i.e., that it be "software-transparent" to the host.
It is an object of the present invention to provide a memory system which provides improved performance as noted above, while being software transparent to the host.
In order that a memory subsystem can be software transparent to the host, it is necessary that it support its own error recovery and data management functions without intervention of the host computer or its operators or programmers.
It is an object of the invention to provide a memory subsystem with its own data storage and management and error recovery functions, such that the operator and/or programmers of the host computer need not even be aware of the memory system's existence.
During typical operation of a data processing system according to the prior art, a host computer reaches a point in a program at which it requires additional data to be fetched from a long-term storage device and brought into main memory. At this point, a "read" command is generated and passed over the channel to the memory subsystem. Similarly, at some point a host computer may desire to write data generated during processing to a long-term memory subsystem; accordingly, a "write" command would be generated and passed over the channel to the memory subsystem. These read and write commands generally may be referred to as system input/output commands or "SIOs". As noted above, the typical long-term memory storage means requires some appreciable time before any given read or write command can be executed due to the latency time inherent in the mechanical system. Further, communication paths between the host computer and the device must be free in order to start the SIO operation. So that the host is not idled during latency, it moves on to another task, while a "queue" of SIOs is generated, if the required communication path is busy. The SIO's are thereafter satisfied by the memory system as soon as communications paths become available. This operation is typically performed under control of one or more "storage director units" which for example in the case of disk drives may control up to eight individual rotating spindles each of which may carry up to 10 magnetic disks, each accessible on either side by 20 read/write heads. It will be appreciated by those skilled in the art that a queue may have a large number of SIO requests waiting at any given time, and that such lengthy queues involve substantial system complexity, for which price and performance penalties must be paid.
It is an object of the invention to reduce the length of such queues to further increase system utilization and performance.
Similarly, when the data subsystem is ready to perform the read or write operation requested, the required communications paths may not be available, since the above mentioned seek and latency operations are actually performed disconnected from the host computer. Accordingly, the desired data which is at a fixed position on the continually rotating surfaces will pass by the head untransferred, requiring an additional full rotation before the next reconnect try. This is termed "RPS miss" time and greatly adds to the delay in processing the required data.
It is again an object of the present invention to reduce this "RPS miss" time.
Systems have been offered for sale in the prior art which purport to solve the problems listed above. For example, Memorex Corporation has offered for sale a device, known as the Model 3770 Disk Cache System, which is to be attached to a single storage director controlling the operation of a number of disk drives. When a "read" request is received from a host computer, the 3770 cache system reads the data from the disk into a solid-state memory and thereafter makes it available to the host. This system has the possibility of saving a certain amount of RPS miss time. However, the 3770 system has certain design defects which are overcome by the present invention. For example, the 3770 system attaches to a single "control module" which consists of specialized electronics that operate under a director and control one to eight drives of a single type. This is undesirable, as many existing data processing systems contain plural types of disk drives, so that it would be desirable to provide a cache memory system which has the capability of improving the performance of all these types of disk drives within a single embodiment.
It is accordingly an object of the invention to provide a cache memory system which is adapted to be connected to a plurality of disk drive types.
Another disadvantage of the 3770 design is caused by the fact that it is connected "beneath" a single director in the data system organization, i.e., on the other side of the director from the CPU. Accordingly, the hardware and software required to implement the cache is bound to a relatively few drives (8 or less). Since a director can control up to 64 drives in a typical embodiment, multiple cache devices must be used in order to provide caching capability to all the drives. Some number of these caches will be idle at any one time, while others are busy. The overall hardware utilization can thus be quite low with this system, and the expense quite high due to the multiple copies of hardware that must be provided to support all drives.
It is an object of the present invention to provide a cache memory system which can be connected to plural directors thus rendering it capable of improving the efficiency of processing several read/write instructions simultaneously, to any of the disk drives connected to the director and in which the cache resources are allocated dynamically to the active drives as required.
New drive interconnection systems have been developed to improve path availability. One such system is termed "dual port" in the industry and provides two alternative connection paths for each device. This system cannot be accommodated by the Memorex system. Such accommodation is an object of the present invention.
Other aspects and objects of the invention will appear to those skilled in the art as the discussion below proceeds. In particular, the requirement of software transparency of the cache memory subsystem of the invention to the host requires, inter alia, that means be provided whereby the cache memory subsystem can be removed from the ordinary data flow if any error occurs in it. Furthermore, the requirement that the cache memory subsystem of the invention be useful with a plurality of differing types of disk drives within a particular embodiment requires that data records of varying predetermined sizes be efficiently accommodated within the cache memory system.